readcounter <= (( std_logic_vector'(readcounter1, readcounter0)));
next_sreg<=m0full;
next_sreg1<=m0empty;
IF ( RESET='1' ) THEN
next_sreg<=STATE0;
BP_dcounter <= (std_logic_vector'("00"));
ELSE
CASE sreg IS
WHEN m0full =>
next_sreg<=m0writewait;
BP_dcounter <= (( std_logic_vector'(BP_dcounter1, BP_dcounter0)));
WHEN m0writewait =>
IF ( (sreg1=m0empty)) THEN
next_sreg<=write0;
BP_dcounter <= (( std_logic_vector'(BP_dcounter1, BP_dcounter0)) + std_logic_vector'("01"));
ELSE
next_sreg<=m0writewait;
BP_dcounter <= (( std_logic_vector'(BP_dcounter1, BP_dcounter0)));
END IF;
WHEN STATE0 =>
next_sreg<=write0;
BP_dcounter <= (( std_logic_vector'(BP_dcounter1, BP_dcounter0)) +
std_logic_vector'("01"));
WHEN write0 =>
IF ( BP_dcounter0='1' AND BP_dcounter1='1' ) THEN
next_sreg<=m0full;
BP_dcounter <= (std_logic_vector'("00"));
ELSE
next_sreg<=write0;
BP_dcounter <= (( std_logic_vector'(BP_dcounter1, BP_dcounter0)) +
std_logic_vector'("01"));
END IF;
WHEN OTHERS =>
END CASE;
END IF;
IF ( RESET='1' ) THEN
next_sreg1<=STATE1;
readcounter <= (std_logic_vector'("00"));
ELSE
CASE sreg1 IS
WHEN m0empty =>
next_sreg1<=m0readwait;
readcounter <= (( std_logic_vector'(readcounter1, readcounter0)));
WHEN m0readwait =>
IF ( (sreg=m0full)) THEN
next_sreg1<=read0;
readcounter <= (( std_logic_vector'(readcounter1, readcounter0)) +
std_logic_vector'("01"));
ELSE
next_sreg1<=m0readwait;
readcounter <= (( std_logic_vector'(readcounter1, readcounter0)));
END IF;
WHEN read0 =>
IF ( readcounter0='1' AND readcounter1='1' ) THEN
next_sreg1<=m0empty;
readcounter <= (std_logic_vector'("00"));
ELSE
next_sreg1<=read0;
readcounter <= (( std_logic_vector'(readcounter1, readcounter0)) +
std_logic_vector'("01"));
END IF;
WHEN STATE1 =>
IF ( (sreg=m0full)) THEN
next_sreg1<=read0;
readcounter <= (( std_logic_vector'(readcounter1, readcounter0)) + std_logic_vector'("01"));
ELSE
next_sreg1<=STATE1;
readcounter <= (( std_logic_vector'(readcounter1, readcounter0)));
END IF;
WHEN OTHERS =>
END CASE;
END IF;
next_BP_dcounter1 <= BP_dcounter(1);
next_BP_dcounter0 <= BP_dcounter(0);
next_readcounter1 <= readcounter(1);
next_readcounter0 <= readcounter(0);
END PROCESS;
PROCESS (BP_dcounter0,BP_dcounter1,dcounter)
BEGIN
dcounter <= (( std_logic_vector'(BP_dcounter1, BP_dcounter0)));
dcounter0 <= dcounter(0);
dcounter1 <= dcounter(1);
END PROCESS;
END BEHAVIOR;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY ieee;
USE ieee.std_logic_unsigned.all;
ENTITY DUOZTJI IS
PORT (dcounter : OUT std_logic_vector (1 DOWNTO 0);
CLK,RESET: IN std_logic);
END;
ARCHITECTURE BEHAVIOR OF DUOZTJI IS
COMPONENT SHELL_DUOZTJI
PORT (CLK,RESET: IN std_logic;
dcounter0,dcounter1 : OUT std_logic);
END COMPONENT;
BEGIN
SHELL1_DUOZTJI : SHELL_DUOZTJI PORT MAP (CLK=>CLK,RESET=>RESET,dcounter0=>
dcounter(0),dcounter1=>dcounter(1));
END BEHAVIOR;